Design Of A 10-bit 10M Sampling Rate Successive Approximation Analog-to-Digital Converter

Successive approximation analog-to-digital converters(ADCs)have medium resolution and medium speed,small chip area and low power consumption can also be achieved in CMOS process.Moreover,it is convenient to make multi-channel conversion.Due to their mixed advantages in resolution,speed,power and cost,successive approximation ADCs are widely applied in wireless communication,industry controlling,medical instruments,and auxiliary analog-to-digital interfaces of micro-processors and so on.A 1.2V,10 bit,10Ms/s low-power successive approximation ADC is designed in this thesis,which features differential input and synchronous clock.Study work can be categorized into 3 parts: After circuit design and simulation,the physical layout design,post-simulation and chip measurement are also finished.The proposed ADC is designed and fabricated in GSMC 0.18 um Mixed Signal CMOS process,occupying 0.8mm×0.8mm.Measurement results show that,its SNDR achieves 59.38 dB at 10Ms/s,thus ENOB is 9.57 bit.