Research And Design On A 12 Bits 100MS/s Successive Approximation Register ADC

The advancement of integrated circuit and digital signal processing technologies are digitizing information processing.Analog-to-digital conversion is essential to obtain analog information in nature,so Analog-to-Digital Converter(ADC)is becoming increasingly important.The diverse applications today put forward higher requirements for the performance of ADC.The low-voltage advanced technology optimized for digital circuits brings many difficulties to the design of analog circuits.Therefore,SuccessiveApproximation-Register ADC(SAR ADC)with high process compatibility and low power consumption has attracted much attention in recent years.The resolution of the SAR ADC based on charge redistribution is mainly affected by capacitance mismatch,the speed is mainly limited by the settling speed of the Capacitor Digital to Analog Converter(CDAC),and the power consumption is mainly from the capacitor array and comparator.However,the matching accuracy of the capacitor is contradictory with the power consumption and speed of the ADC,which limits the comprehensive performance of the SAR ADC.In this thesis,a CDAC with IMCS structure is used to ensure high sampling accuracy and achieve low power consumption.The use of redundant bit reduces the accuracy requirement of DAC setlling.The power consumption characteristics and capacitance matching of the structure are analyzed in detail.The capacitance mismatch calibration technique based on detection of the comparator's metastability can effectively improve the linearity of the ADC,so the unit capacitor can be very small,which further reducing power consumption and chip area.A high-speed bootstrapped switch with high linearity is designed to ensure the linearity of the sampled signal.The resolution of the comparator directly affects the resolution of the ADC.This thesis uses a low-noise two-stage full dynamic comparator with offset calibration.The main factors affecting its speed,noise and power consumption are analyzed in detail.In order to implement the capacitance mismatch calibration technique,this thesis proposes a metastable detection circuit suitable for high-speed comparators.In addition,high-speed and low-power SAR control logic can optimize DAC settling time and comparator operating time.In this thesis,a 12 bits high-speed SAR ADC with a sampling rate of 100MS/s is designed using a 40 nm process.The simulation results show that when the input signal frequency is 0?50MHz,the ENOB of the ADC is higher than 11.5 bits,the SFDR is higher than 90 d B,the average power consumption is 4.71 mW,and the figure of merit is 16.3fJ/conv-step.