A Study Of SPARC V8 ISA Oriented Processor Model Verification Technology

With overhead of SoC, especially overhead of processor is increased, numbe r of errors that may exist in the chip design sharply increase, so the industry has urgent need for new verification methodologies and new tools to improve efficiency of the verification towards So C. In recent years, the time proportion spent on the verification in the project continues rising, so it is necessary to research technology which has important significance to enhance efficiency in finding design errors as verification occupies most of the processor project.Firstly, this thesis completes functional verification of SPARC V8 ISA processor model and four kinds of AMBA AHB bus interface which connect to the processor model. This paper also analyses architecture of SPARC V8 ISA and its AHB bus interface, based on architectural features and elements o f the processor hardware design, elaborates the verification strategy based on functional point, and builds UVM-based verification platform for bus interface model. For the four processor AHB bus interface model, functional point extraction is completed, and the models are mounted to UVM verification platform whose interface is designed based on DPI co-simulation technology. This new interface can co-simulate System C model-under-test and System Verilog verification platform; compared with official library, this interface has lower overhead, and faster simulation speed.Secondly, for SPARC V8 ISA processor architecture, the SPARC V8 ISA is verified including single instruction, combined instruction, random instruction verification as well as Mibench and Dhrystone test programs. Results are given to verify the results and to be analysed, and all indicators meet expectations.Finally, based on dynamic neural network, a new stimulus generation technology is tried realizing in NARX network structure. the implementation of a rational quantify strategy is for disassemble code of Mibench as training samples, using Bayesian regularization algorithm to complete the training process. By generating stimulus sequence, quantitative comparison of performance with the technology using the traditional pseudo-random stimulus generation technology is done in methods of series and pattern lookup, which demonstrates the application of this new technology can be more effective in finding design errors and improving verification efficiency by nearly 15%.