Research On Embedded Systems Simulation Platform Based On SPARC

The embedded system has been widely used in many areas such as control, aviation and communications. Since the increasing complexity and size of embedded software, the embedded software testing is becoming more difficult than before. For decades, the embedded system emulator has been an efficient method for the embedded software testing, which greatly improves development efficiency, reduces the intensity of test and also avoids a large amount of faults in the process of designing. The SPARC microprocessor is widely used in the field of aerospace for its high scalability. This paper will focus on the SPARC processor and promotes a simulation platform of the embedded systems based on this processor architecture.The partial outcome of this program is a cycle-accurate instruction set simulator:the VirtualSPARC. It contains the arithmetic unit IU, MMU and the interrupt system module. The VirtualSPARC also integrates I2C, keyboard, peripheral simulation unit and supports single-step debugging, breakpoint debugging. For the reliability testing of the platform, random test and benchmark test are traditional test methods. Apart from that, this paper includes some research on the FPGA-based hardware and software co-verification method as well as the test case generation method based on the Markov usage model. This test case generation module helps to quickly locate the system security leaks, reduce software development costs and improve the efficiency of the test. At last, this paper promotes a performance assessment method based on queuing theory model. The dynamic performance indexes of the system are obtained, including interrupt loss rate, the average response time and the system throughput which guide the embedded system hardware and software design.The VirtualSPARC simulation platform proves to be of high accuracy and high scalability. The theory of visual processor simulation, the dynamic verification method of embedded software and the performance evaluation based on queuing theory provide a failure controlled test way to reduce the complexity of the embedded software and hardware design.