SPARC V8 For Software And Hardware Co-simulation Environment Of SOC Design

With the increasing degree of circuit integration and the appearance of deep submicron technology, it is an inevitable trend for IC to SOC and the21st century will be the era of SOC. The design of SOC is more and more complex, and the scale is bigger and bigger with the improving requirements of the market application. The corresponding difficulty and complexity of SOC verification is also increasing. The key technology of SOC verification——collaborative simulation technology of software and hardware, is more and more important. A good collaborative simulation environment of software and hardware can find the error which exists in the early design. It can also improve the test coverage and increase the probability of first-time Silicon Success.Based on the embedded processor of SPARC V8, SOC is increasingly used in aerospace, military, and industrial control and so on which control national economy and national defense construction. In the manned spacecraft and control applications where require high real-time and stability, the reliability and completeness of validation in SOC design is higher and higher. So the collaborative simulation technology of software and hardware for the embedded processor of SPARC V8is becoming more and more important. At present, the main embedded processors in market (such as MIPS、ARM) have their own collaborative simulation tools of software and hardware. However, the verification of SOC based on the SPARC V8doesn’t have the corresponding tool of collaborative simulation and it is difficult to carry out the collaborative simulation of software and hardware. So there is a great significance that research and design the collaborative simulation environment of software and hardware based on SPARC V8for the verification of domestic SOC.This paper designs a collaborative simulation environment of software and hardware for SPARC V8and realizes its collaborative simulation and verification. The following aspects are included in this paper.1Discuss the traditional verification technology of integrated circuit fully, study the verification method of SOC deeply and analyze the collaborative simulation technology of software and hardware emphatically which is the leading verification technology of SOC in industry. The foundation of designing the collaborative simulation environment of software and hardware is understanding the principle of collaborative simulation technology. 2The embedded processor LEON2which based on SPARC V8has open RTL-level source code. The IP core of domestic SPARC V8research in this paper is modified and clipped on the basis of LEON2. The RTL-level source code of this IP core executes the software program as a processor model in collaborative simulation environment. So it is necessary to analyze the structure of SPARC V8and LEON2deeply before designing the collaborative simulation environment. According to constructing the prototype verification platform of LEON2based on FPGA, the paper carries on the LEON2kernel’s hardware debug and software verification. In hardware debugging process the paper analyze the whole processor’s architecture and the functions of each module. In the process of software validation the paper analyze the internal data flow among each functional module.3This paper puts forward a whole scheme of software and hardware collaborative simulation and designs its overall framework. The collaborative simulation environment uses the RTL-level source code to simulate the processor core in MODELSIM. The software program is written in software debugger SPE-C. The key points are realizing the hardware simulator’s interactions with the data of the software debugger, making the software programs executed on a processor core and making the waveforms of software and hardware synchronized according to the instruction.4According to the overall framework of collaborative simulation environment, the paper designs the hardware module and software module which are needed by the environment, realizes the communication between the hardware emulator and software debugger and establishes the software and hardware collaborative simulation environment.The collaborative simulation environment makes use of the RTL-level source code to simulate the processor core in this paper. Comparing with the simulation of current common processor and instruction-level model, its results are closer to the real target system. It reduces the repeated investment in hardware and save the resources. Besides, the debugging performance is high and the observability of the internal signal is extremely strong. The establishment of the simulation environment provides the platform of software and hardware collaborative simulation for the SPARC V8’s SOC verification. It also provides theoretical and practical basis for the software and hardware collaborative simulation of SPARC V8’s SOC. There is an important significance for improving the domestic SOC’s ability of independent innovation.