Research On Realization And Optimization Of Algorithm Of Radar Signal Processing Algorithms Based On BWDSP1042

CETC-38 launched the multicore radar signal processing chip BWDSP1042 in the major project "Core electronic devices, high-end general chips and basic software products". BWDSP1042 is CETC-38’s development of radar-oriented high-performance multicore digital signal processors followed by and based on BWDSP100, with highly integrated command system, the modular structural program research and higher parallelism. This paper carried out the research and implementation of a number of algorithms of radar signal processing based on BWDSP1042. The main contents are:1. The research and implementation of FIR algorithm based on different points and different data formats of BWDSP1042Through the familiarity with BWDSP1042’s internal structure and the instruction scheduling principle of BWDSP1042 processor software platform ECS (Efficient Coding Studio), this thesis makes reasonable arrangements of BWDSP1042 internal registers and arithmetic units, and gives the best solution, so as to maximize the utilization of computing components and to reduce the program cycle times under the premise of a relatively small amount of computing components needed. This thesis gives the specific processes, writing, call, the actual cycle and the theoretical cycle of FIR filter program research in BWDSP1042.2. The research and implementation of FFT algorithm based on different points of BWDSP1042When doing the FFT algorithm, this research uses of-2 decimation in time to extract FFT algorithm, efficient FFT algorithm based on partial orthotopic in reverse order and peculiar mode eight addressing modes, which has greatly improved the efficiency of the FFT algorithm. Similar to FIR algorithm, this research reasonably arranges internal registers and arithmetic units of BWDSP1042, to improve the utilization of arithmetic units and reduce program’s execution cycle. The research gives the specific processes, writing, call, the actual cycle and the theoretical cycle of FFT program research in BWDSP1042.3. The validity check of algorithm of the researchThrough an analysis of the total number of components required for a variety of algorithms and the number of internal arithmetic units of BWDSP1042, it is concluded that the ratio of the theoretical cycle of algorithms to the actual cycle of algorithms of this research is 80%, i.e, the arithmetic units of BWDSP1042 can be fully and rationally used. Compared with the period of internal library and run-time of other mainstream high-performance DSP chip (such as the TMS320C6678, BWDSP100, ADSP-TS201), and by doing error analysis with generate data for the standard deviation compared with the MATLAB, the results show that after the algorithms of this research’s fully use of their arithmetic units, the cycle of algorithm and time is greatly reduced compared to TMS320C6678, ADSP-TS201 and BWDSP100 (and period ratio to ADSP-TS201 cycle is up to 15.77), a similar error.This research has almost completed the utilization of computing components, improved the efficiency of the algorithm, given full play to the advantages of BWDSP1042’s arithmetic units, which is of great significance to the promotion of the performance of radar signal processing chip that independently researched and developed by our own country.