Research On Condition Code And Register Allocation Optimization In Co-design Emulation

With the rapid development of microelectronic technology, a lot of processors of new architecture are emerging. Research on porting the abundant software originally compiled for x86 platform to new processors is becoming an effective way to achieve the application and popularization of the new processors. The x86 system emulation based on hardware/software co-design technique by adding special hardware resource into underlying processor can reach greater efficiency than pure software emulation, thus achieve the running of the x86 OS and applications on new architecture processors efficiently and transparently.This paper analyzed the key factors that restricting the performance of x86 system emulator ARCH-BRIDGE, and based on the open source processor OpenRISC 1200 as the host machine, a co-design x86 system emulation platform named CoAB(Co-Designed ARCH-BRIDGE) was constructed to research on the approaches of improving the performance of x86 system emulation; To reduce the emulation cost of x86 condition codes, a co-designed condition code optimization approach based on direct register mapping and the EEFLAG(Emulated Eflags) controlled by custom instruction was presented. The complicated software read or modification operation of x86 condition code was transformed into a single customized instruction, and it improved the efficiency of condition code emulation; To reduce the expand rate of translated code and the cost of context switching between Translation Engine and Execution Engine, a co-designed register allocation optimization approach based on register mapping, custom instructions and shadow registers was presented. The operation to some emulated source registers in memory was transformed into the operation to local registers by optimization of register mapping, and it shrunk the expand rate of translated code. The backup and restore operation between engine switching was reduced to 2 customized instructions by optimization of custom instructions and shadow registers, and it improved the efficiency of engine switching.Evaluation showed that the co-designed condition code optimization approach could correctly complete the translation of x86 instructions, read or modification of the EEFLAG, and shrunk the expand rate of translated code by a degree up to 25.4%; and after applying co-designed register allocation optimization, the expand rate of translated code was reduced by a degree up to 24.7%, and the running time got a speedup of 1.49 mostly.