Investigation On Optimization Techniques Of Register Spilling For Vector VLIW Processor

The hardware facilities of modern processor architecture already has a very good performance, especially vector VLIW processor has both scalar and vector processing unit. Different from superscalar, super-pipelining and other high-performance architectures, instruction scheduling, dependency checking, and such works of VLIW are implemented by corresponding compiler. Therefore, the compiling optimization technique is the key to exploit the high performance of processors, register allocation is responsible for replacing the symbol registers in intermediate code with the physical registers of the target machine, and stores operands into registers as effectively as possible to improve the efficiency of execution of the code. In order to solve the problem that limited number of registers can't meet the number of candidates in register allocation, some candidates have to be stored in memory temporarily by register spilling. To optimize the register spilling can improve code quality, and rationally use the register resources. Combining vector VLIW processor features, this article will investigate the following three aspects on register spilling on the basis of graph coloring method.1. Copy instruction optimization. In the context of vector architecture, copy instruction where the webs corresponding to its source symbol register and aim symbol register are to be spilled is considered and the corresponding copy instruction optimized method is designed. When the definition of the web corresponding to aim symbol register is only existed in the copy instruction, two storage spaces are designed to store the spilled data for scalar and vector data cases, respectively, and corresponding scalar or vector instructions will be corresponding inserted to save or recover the spilled data in this method. This can achieve the same goal as using the copy instruction. This optimization method helps to reducing scalar or vector copy instructions and to save storage resources.2. Optimization of definitions spilling or uses recovery in loop. There are definitions or uses of webs that will be spill. For loops of vector architecture, an optimization method for spilling handling is designed. For the loops in which spilling instructions should be inserted for definitions or uses, this optimization method analyzes the live variables of scalar registers and vector registers. If the number of them is no more than the number of corresponding available physical registers, theplace of spilling definitions and that of recovering uses will be out of the loop. This optimization method can reduce scalar or vector data spilling and recovery instructions in loops, and improve the code's execution efficiency.3. Optimization of storing spilled data. Spilled data of register allocation candidates need to be stored into storage when spilled. For this problem, in this article we investigate the problem that spilled data doesn't have to be stored in different storage units and design corresponding spilled data storing optimization algorithm.By analyzing whether live ranges of register allocation candidates which need to be spilled are overlapping, the algorithm judges whether they conflict with each other from both the scalar and the vector aspects. Spilled data that don't conflict with each other will be stored in the same storage space. This optimization can save storage resources in register allocation, and the effect is more obvious for the vector instruction case.