Control Processing Chip Instruction Set Control Register Management Techniques Designed To Study

The technology based on instruction set control and register optimization is important to realize the high performance design for micro-control unit and micro-processing unit. The target of this research subject is to deeply research the instruction set architecture design technology and register optimization technology. Basing on the research, we have designed the instruction pipe-line architecture and register optimization for the 8-bit micro-controller. Finally, the function and timing of the design have been verified in the micro-controller system.The ultimate goal is to tape out.The research on instruction set control technology is divided into two parts .One is the instruction set architecture, the other is instruction pipe-line. Now, instruction set architecture mainly includes CISC and RISC. The characteristic, advantages and disadvantages of them are analyzed. Instruction pipe-line is important technology, which is good for realizing high performance. Pipe-line depth and relativities which includes data relativity,control relativity and hardware relativity ,are analyzed . The super pipe-line, superscalar and VLIW are also refered to, which are important developing technologies at current.With regard to the research on register configuration and optimization, firstly, how to configure registers for micro-control unit and micro-processing unit is analyzed. Secondly, the two kinds of register optimization technologies, which are register optimization based on compiler and register window, are deeply researched.Based on above the theory and technology research, we have designed the instruction pipe-line architecture and register optimization for the 8-bit MCU. PIC instruction set is the typical RISC.So PIC instruction set is chosen for the 8-bit micro-controller.The pipe-line architecture is designed for the MCU. The key pipe-line circuits, including PC, IR, ID and ALU, are designed and verified. Registers of the mcu are also configured. The register circuits are designed and the register storing structure is optimized by distributing them in two banks. With the simulation tools including MPLAB IDE v7.20 and Spectre-Verilog, the function and timing of the design are verified in the MCU system. The layout work is past to layout design team and tape out finally.