Design Of 433MHz RF Front-End Circuit

RF chip is the core building block of the circuits of modern communication systems, which directly determines the performance of the communication quality of the whole communication system. RF front-end receiver circuit is an important component of the radio frequency chip module receives link, and their power occupy 30%～40% of total chip power consumption. The research on reducing consumption of RF front-end circuits is important to reducing the consumption of the entire transceiver chips.This thesis designed low-power RF front-end receiver circuit, working in 433MHz band FSK receive mode consist of a low noise amplifier and down conversion mixer. This thesis gives the research status of the RF front-end circuit in the recent years and describes the basic principles of a low-noise amplifier and mixer with the key performance parameters, designed the circuits by the requirement of system:in the design of low noise amplifier, let PMOS transistor stack on the NMOS transistor as current-reuse method in order to avoid using dc negative feedback circuits, as well as a good bias circuit has been given; the equivalent circuit transconductance can be improved by the improved capactive cross-coupling technology, as well as the noise performance of the circuit. In the mixer design, for the low-noise amplifier gain shortage, adding an amplifier, combined with folding design method, this stage and the mixer transconductance are located at the same branch constituting the current reuse to reduce the power consumption, using the current bleeding technology reducing the current of the switching MOS transistor, by this a good noise figure can be given; the resistor network giving on the output of Mixer are used to control the gain of the circuit.In this thesis, the schematic and layout has been designed and simulated in SMIC 0.18μm technology. The simulation show that, in the 1.8V supply voltage, the dc current is 2.42mA, the circuit can have 49.7dB in the large gain module,45.03dB in the low module. IIP3 is-19dBm, noise factor is 6.75dB. The result reached the design specifications in the design.