Study Of Novel Integratiable Lateral Power Devices With Low Specific On-resistance

As the core device of the SOI power integrated circuit design, the trend of the SOI lateral power devices’ development is to improve the breakdown voltage(BV) and reduce the specific on-resistance(Ron,sp). A long drift region and lightly doped level are necessary in order to improve(BV) for the conventional Lateral Double-diffused MOSFET(LDMOS), however, it inevitably increases the Ron,sp. The contradictory relationship is also known as the “silicon limit”. In this paper, three novel device structures are proposed to improve the tradeoff between BV and Ron,sp.(1) A low specific on resistance SOI LDMOS with double trenches. The oxide trench in the drift region realizes an enhanced RESURF effect, which increasing the doping concentration, and folds the drift region in the vertical direction, led to a reduced cell pitch and Ron,sp. The trench gate which extending to the box layer reduces the on-resistance by the accumulate electron layer and can also work as dielectric insulation. The simulation results shows that a 6.5?m DT SOI LDMOS can achieve the BV of 233 V and the Ron,sp of 3.3 m?·cm2. Compare to the conventional SOI LDMOS with the same cell pitch, BV increased by 150%,and the Ron,sp reduced from 4.8 m?·cm2 to 3.3 m?·cm2, reduced by 31%. The process and the layout of the device are successfully designed. The test results show that BV of the samples are between 180-190 V, and achieve the goals of BV greater than 150 V and output current is up to 0.5A.(2) A SOI LDMOS with Double Sided Charge Trenches(DCT SOI LDMOS). On the blocking state, charges are collected in the DCT and located at the oxide /polysilicon interface, which sharply enhances the dielectric field strength, the oxide trench accommodate the potential line in the drift region, increase the electric field both in the SOI layer and the BOX, thus increases the breakdown voltage. The heavy doped polysilicon are advantageous to collected charges and the one near the source can work as the body contact as well. The simulation results show that a 3.5?m DCT SOI LDMOS can achieve the BV of 158 V and the Ron,sp of 1.08 m?·cm2. Compare to the TG SOI LDMOS with the same cell pitch, BV increased 105 V, compare to the TG SOI LDMOS with the same BV, the cell pitch reduced by 70% and the Ron,sp reduced by 76%.(3) A low on resistance trench type SOI LDMOS. Two P doped regions are introduced into the drift region, a P type pillar is located at trench side wall near the p well,and a buried P type island is located at the interface of the Box. Both of the p type regions modulate the potential distribution in the drift region, result in increasing BV. It also led to the doping concentration increase which reduces the on resistance effectively. With the cell pitch of 8.5?m, the proposed device can achieve the Ron,sp of 6.3 m?·cm2 and the BV of 236 V. Compared to the conventional trench type SOI LDMOS, the Ron,sp reduced by 40% and the BV increase by 34 V.