Design Of Novel Low Specific On-resistance LDMOSfets With Trench Gate

How to relieve the contradiction between the breakdown voltage and the specific on-resistance is always a hot topic in the field of power LDMOS(Lateral Double-diffusion Metal Oxide Semiconductor).As a kind of structure which can effectively improve the performance of the device,the trench gate is widely used to design of power LDMOS.Based on the trench gate technology,three novel LDMOS structures at different voltage levels are proposed,in order to achieve a better tradeoff between the breakdown voltage and the on-resistance.1.A 100V-classs SOI LDMOS device with extended gates(ETG SOI LDMOS-Extended Trench Gate Silicon-On-Insulator)is proposed.The gate in the P-body forms a three-gate structure,and the extended gate part locates the two sidewall of the drift region.On the one hand,the three-gate structure effectively extends the channel width and thus reduces the channel resistance;on the other hand,a capacitor consisting of the extension gate,the oxide trench and the drift region,cause electronic accumulation layer in the on state,and depletes the drift region in the blocking state to increases the drift region doping,both of which effectively reduce the drift resistance.The simulation results show that BV=94V and Ron,sp=0.34 m??cm2 are obtained for the ETG SOI LDMOS.Compared to those of the Con(Conventional)SOI LDMOS and SJ(Super Junction)SOI LDMOS at almost the same breakdown voltage,the on-resistance decreases by 67.8% and 54.7%,respectively.The new structure gets a better tradeoff between breakdown voltage and the specific on-resistance.2.A novel SOI LDMOS device with N-type Buried Layer(NBL)and Trench Gate Trench Drain(TGTD)at 200V-class(NBL TGTD SOI LDMOS)is prensent.The combination of the trench gate and trench drain greatly reduces the current path length and spreads the conduction area in the drift region,thereby effectively reducing the resistance.N-type buried layer can improve the electric field in the buried oxide layer and optimize the electric field distribution in the lateral direction,thus improving the breakdown voltage.For the NBL TG LDMOS breakdown voltage of 221 V and the specific on-resistance of 3.0m??cm2 are realized by simulation,the breakdown voltage is increased by 15% and the specific on-resistance decreased by 36% compared with that of conventional TG SOI LDMOS.3.A novel LDMOS device structure with P-type Buried Layer(PBL)and Trench Gate(TG)at BV of 700V-class(PBL TG LDMOS)is investigated.First,the trench gate not only optimizes the current path in the on-state,but also modulates the electric field distribution as well as depletes the drift region in the blocking state.Second,the P-type buried layer modulates the electric field distribution,so as to prevent premature breakdown at the end of the trench gate;furthermore,the P-type buried layer depletes the drift in the blocking state.The effective combination of the trench gate and the P-type buried layer improves both the brealdown voltage and the specific on-resistance.BV = 775 V and the Ron,sp = 119m??cm2 are obtained for the PBL TG LDMOS.Compared to conventional LDMOS with the same device dimentional parameters,the PBL TG LDMOS increases the breakdown voltage by 47% and reduces the specific on-resistance by 53.7%.