Elastic Design And Verification Of Micro-controlling SoC For Digital Electrical Signal Processing

With the development of integrated circuit, SoC(System on a chip) has gradually become the mainstream direction of embedded systems. The SoC integration is improved continuously, and the function has become more and more complex. It brings us the great convenience in the communication, home appliances, industrial, medical and other fields. But it also puts forward higher requirements to the system size, design cycle, and the production cost. Therefore, this thesis studies the elastic design method of micro-control SoC for digital electrical signal precessing, and builds a multi-level hardware/software co-verification environment to improve the efficiency of verification. Finally, the SoC system is applied to digital appliance.The main contributions of this work are listed as follows.1) The elastic design method of SoC systems is proposed. In this method, elastic function parameters and interface parameters are used to design the whole structure of SoC systems. The internal size and function can be adjusted. At the same time, the on-chip bus and peripheral IP modules are designed in detail for the basic functional requirements of SoC systems.2) A set of RISC instruction system and the five-stage pipeline architecture are designed. In order to meet the needs of digital appliances, this instruction system has some characteristics, such as higher efficiency, small fluctuation complexity, fast execution speed and small occupancy resources. Five-stage pipeline architecture effectively improves the execution efficiency of instructions, and also enhances the work speed of SoC systems.3) A multi-level hardware/software co-verification platform is built. The software simulation environment of the platform provides the interfaces that transmit verification data with hardware test environment. In PC side, the designers can control and debug stimulation or response signal of FPGA. Through packaging the internal data structure, we can avoid unexpected error modifications, and increase the stability of the multi-level hardware/software co-verification platform.In addition, a complete design and verification of the SoC system is completed, and it is applied to the solution to digital appliances. In this way, we improve the design efficiency and implementation effect of the field.