Design And Implementation Of High-speed Data Buffer And Data Switch

As the informationization level of modern society more and more high, all kinds of information meeting the demand of people are in a sharp increase. High speed, reliable, and real-time transmission of huge amounts of information becomes a hot spot of the researchers. Because of parallel transmission technology is widely used in the industry before, the existence of the clock and data cannot be precise alignment, PCB layout and signal crosstalk between serious defects such as difficulty, makes the transmission rate of ascension has reached design bottlenecks, but still cannot meet the increasing requirements at a high speed. While in recent years the emerging technologies of high-speed serial transmission has a higher bandwidth, stronger anti-interference ability and the advantages of more convenient and easy to use interfaces, it is fast becoming the industry’s most popular design. In the process of the realization of a high-speed serial interface, a growing number of developers prefer to use the field programmable gate array(FPGA), which has good reconfigurability and easy to realize, and make the FPGA technology is a kind of high cost performance.On the implementation platform constructed by Xilinx FPGA, this paper has completed the design and implementation of high-speed data acquisition and storage system, on the basis of a deep research about high-speed serial transceiver Rocket IO GTX. The system with the high-speed data cache constructed by Virtex-6 series FPGA XC6VLX240 T as the data switch matrix, can carry on the shunt to the RF signal sampled by ADC, and real-time deposit in disk array with SATA interface, and download the storage data through a dedicated high-speed interface, and read data back to the local computer and user’s computers. This paper’s main research results are as follows:1.Designed and implemented high-speed data serial interface. According to the characteristics of the high-speed serial transmission technology, in depth study and analysis the Rocket IO GTX composition structure and working principle. Rocket IO as precise component, the internal structure and parameters configuration is very complex. Using common way of calling the underlying primitives is cumbersome and error-prone, while with the aid of the IP core development guide provided by Xilinx company, the design becomes simple and easy. First of all, the loopback test has been carried on GTX. Test showed that the correct parameters configuration, to ensure the establishment of thebasic communication link. Secondly the intercommunication between GTXs of different FPGAs has been carried on. Because the GTX works under a high clock frequency control, it is very strict to the requirement of the clock. Therefore the clock configuration need further correction, driven by specific reference clock routing approach. Through the actual test find that Rocket IO stable transmission speed can reach 3 Gbps, meeting the requirements of the system.2.Designed and implemented high-speed data cache and switch matrix. The acquisition module of the front end of this system and the disk array of the back end of the system varies in data rate, therefore the data rate conversion and distribution control must be carried on. Asynchronous FIFOs have been used to match data rate. The concrete realization method of the high-speed data cache and switch matrix has been analyzed and designed, including the distribution and combination of high-speed data, and the actual transmission effect has been tested on the hardware platform. The whole source code has been written in Verilog HDL, and the function simulation and hardware testing have been carried on. Test results show that the module functions correctly and operates steadily, meanwhile meeting the requirements of the system.