Research And Design On A Low-power SAR Analog-to-Digital Converter With 1.5-b Redundancy And Acceleration Structure

Analog-to-Digital Converter (ADC) is an important part of mixed signal integrated circuit. Design of high speed and high resolution ADC has always been a hotspot in research among the world. This kind of ADC is extensively applied in radar systems, mobile communication and so on. In this thesis, a low-power Successive Approximation (SAR) ADC is designed and realized. Multiple techniques based on conventional SAR ADC have been proposed for solving major problems faced in design of high speed and high resolution ADC. Among them,1.5-b acceleration technique improves the sampling rate by establishing redundancy for both offset and settling on the conventional SAR structure. Besides that, a new method in circuit and layout design of bridging capacitor in the capacitor array is proposed in this thesis which effectively eliminates the non-linearity caused by parasitic capacitor. The improvement brought by the new techniques are deeply analyzed in this thesis. Finally, a prototype 12-b 50-MS/s SAR ADC is fabricated using 65nm CMOS process consuming only 0.52mW at 50-MS/s sampling rate and 1.2-V supply voltage. The chip achieves an SNDR (Signal-to-Noise-and-Distortion Ratio) of 57.4dB, and a FOM (Figure of Merit) of only 17.9fJ/conversion-step. The FOM is quite outstanding comparing to ADC of similar performance proposed in world’s top conference and journals of solid-state circuit.