System Verilog Assertion Based Functional Verification

As a SoC, Garfield has some typical characters. It is based on AMBA protocols and there are many functional models in Garfield chip. These characters bring many challenges. Functional verification is one of the challenges. It has become a major bottleneck in the IC design process. The most difficulties of IC functional verification are as follows: the building of testbench, the reusability of verification environment, the observability and the controllability of verification process.Currently, we use the constraint-random method to verify our functional model. The verification engineers make the constraint according to the system specification, input the stimulus to DUV and check the result in the output. The advantage of this method is that stimulus could be generated easily and quickly. However, there are still some shotcuts in this method: costing simulation times, finding bugs effectivelessly, and poor observalility.So we introduce the Assertion based verification to improve our work method. Firstly, we introduce the primary functional verification methods and analyse the advantages and disadevantages of these methods. Secondly we discuss the process of Assertion based verification in detail. As a fresh method, many organizations and corps developed languages to support it.In this paper, we use the SystemVerilog Assertion to implement it because of its convenience and usefulness. Then we use the constraint-random method and Assertion based method together to verify the Garfield Chip. Through this way, we make the verification environment more reusable. The observability and the controllability have restricted the efficiency of functional verification. To improving the verification speed, we introduce a auto-assertion interface and the assertion monitors could be added in RTL codings automatically. The auto-assertion interface speeds up the whole verification process.Finally we record the verification results and anlyse the bugs and verification times. It shows that many bugs are found by using the conbined method this paper discussed. It also shows that our method is quite save time in the IC design flow.