The Design Of Modular Multiplier And Quaternary Point Multiplication

As the two most commonly used public key encryption algorithms, RSA and ECC play an important role on security chips. The security chip is integrated in visa, insurance card, ID card and so on, and also used on privacy protection and authentication, which is an important way to realize the information security in practical application. With the extensive use of security chips, an effective hardware implementation of ECC and RSA is urgently needed because of its vital role on improving the running efficiency of the security chips. As is known that Modular exponentiation is the key step of RSA while the point multiplication on the elliptic curve by operation is the main operation of ECC.Firstly, this dissertation introduces the basic principle of RSA and some algorithms used in the implementation of RSA. Then a deep research and design of some important parts,including Random Number Generator(RNG) and modular multiplier, was given. Our work is as follows.? A feasible hardware implementation of RSA is presented, including the RNG by a circuit of chaos and the modular multiplier using a Montgomery modular exponentiation combined with bit scanning. And the feasibility was proved on the security chip test.Next, a detailed discuss on the hardware implementation of ECC is given. A feasible implementation and improvement is given in order to solve the problems of the slow running speed, high resource occupation and so on. Last, this dissertation gives a hardware implementation of those algorithms and runs a detailed test. The main innovatory results are as follow.? A quaternary coding circuit is introduced based on the binary sliding window method. After a quaternary coding of the big number, we use the sliding window to do the point multiplication. It makes a 15% speed up when the length of data is 160. This improvement was also implemented and verified on hardware.