Research On Reliable Chip-Multiprocessor Against Soft Errors

Continuous technology scaling down led to dramatically increasing transistor integration density, and made chips much faster, but also led to lower supply voltage. Howerer, microprocessors are becoming more vulnerable to soft errors induced by energetic particle strikes, such as high-energy neutrons from cosmic rays, and alpha particles from decaying radioactive impurities in packaging and interconnect materials. Besides, CMP (Chip-multiprocessors) were proposed to counter the challenges of ILP (Instruction Level Parallelism) wall, power wall and memory wall and have become the new mainstream microprocessor architecture. So, soft errors have become a key challenge in chip-multiprocessors design.To protect against soft errors, error checking code, redundant computing and vulnerability characterization technology have been used to improve reliability of CMP. But all these methods have some disadvantages and limitations. This paper focuses on disadvantages and limitations of redundant computing and vulnerability characterization technology, and tries to optimize these technologys.The current RMT (Redundant Multithreading) technology has some disadvantages. Soft errors detection and recovery unit is fixed and very large, which is the life time of a thread. Fixed unit is not only inflexible, and error recovery must re-execute the entire thread. To solve this problem, this paper presents TxCMP (Transactional Chip-multiprocessors) architecture. The TxCMP takes use of Transaction as the unit of soft error detection and recovery, and a transaction is composed by a number of machine instructions while the count of instructions can be flexibly configured. Furthermore, TxCMP provides native support for error detection and recovery. In addition, in order to reduce the overheads of error detection and recovery, this paper presents two optimization schemes, which are early transfer scheme and speculative transaction execution scheme.Increasing on-chip cache sizes make caches the major consumer of the processor chip area, so cache confronts with the most of soft error attacks. As well as cache is critical in memory hierarchy. So, it is very important to improve the reliability of CMP cache.Current vulnerability characterization analysis is limited to single-core processor or CMP with MESI cache coherence protocol. In order to comprehensively analyze the influence on LI Dcache vulnerability by varying CMP cache configures, this paper modifies the existing cache vulnerability analysis model which is called as the life time model. The modified model can be applied to a variety of cache coherence protocols. And then, by experiments, this paper quantifies the influence of various CMP cache configures on the vulnerability to soft errors. Eventually, an optimization for CMP with MOESI protocol is proposed, to reducing the CMP cache vulnerability in the premise of minimize the loss of CMP performance.