Research And Implementation Of Concatenated Code Based On FPGA

As an important technology to ensure the reliability of data communication, errorcorrection coding is widely used in deep space communications, storage systems, anddigital television broadcasting system and the like. With the development of informationtechnology and coding theory, a single coding method has been difficult to meet certainsystem requirements, so in practice, the error correction system is often used moreconcatenated coding mode. The main subject of study and implement the RS code,interleaving code and convolution code is intertwined cascade of concatenated codingsystem.This paper first introduces the research background, significance and status ofdevelopment issues of error correction code, and then analyzed several common errorcorrection code, based on the advantages and disadvantages of different errorcorrection code and the actual needs, discuss the choice of RS codes, interleaving depthconvolutional code parameters and select a concatenated coding scheme developed,then introduced the RS code, a convolutional code, encoding and decoding principlesof the interleaved code, then the method given in the FPGA module and the simulationresults.In this paper, the BM algorithm used in solving the key equation has beenimproved, simplified operations. Convolution decoding part of the study of the Viterbidecoder implementation of each module and part of the module presents an improvedmethod.Finally, the simulation program to correct burst errors and random errors ability toprove the correctness and feasibility of the design.