Research And FPGA Implementation Of Channel Code In DVB-T System

In the digital communication systems, when digital signals transmit in the channels, the receiver will get fault data inescapability because of the noise and the variety of channels. In order to reduce the error codes and improve the quality of received codes, we must adopt error control coding. Error control coding is very important especially to the digital video communication system with high bit rates and high qualities in order to provide excellent images.The paper adopts the error control techniques in the DVB-T system which is designed aiming at the digital video communication system. The paper provides the scheme of combining error-correction coding with interlace technology which is the cascade of RS(204, 188, 8) shortened codes, convolutional interleaving and convolutional coding. The design of parameters in every technology provides convenience for MPEG-2 transmission stream (TS stream) and it make the frame construction in transmission stream and the synchronization byte keep unchanged after coding, and then the capture and tracing synchronization become possible.At first the paper simply introduces error control techniques, DVB-T system and the method of FPGA implementation, and then describes the coding and decoding of RS(204, 188, 8) shortened codes, convolutional interleaving and convolutional coding. And at the same time the paper indicates the hardware realizations of every technology and especially emphasizes on the hardware implementation of RS decoding. The RS decoding includes four modules: the computation of syndrome, the iterative of BM, Chien search and the error computation. The paper describes the scheme of circuit design for every module and gives results of every simulation. At last, the error control system is applied to a digital video communication system which has constant output rate and we add the design of interface circuit and speed control according to the requirement of the system.