Design And Verification Of64-bit RISC-P Architecture Processor Based On Fast Prototype

Processor model plays a significant role in the fields of Design Space Exploration,SW/HW Co-verification, Application Special Instruction Processor design and so on.For the purpose of searching for the optimal balance between target demand and realisecosts, architecture designer needs to evaluate many processor architectures, processorarchitecture model should be descriped conveniently and rapidly;software developerneed to develop and debug corresponding system software and application softwarebefore the processors are tapped-out, then work-well hardware model is an essential partof development environment.What is more,verification team need to evaluate theavailability and realize-costs of model from the aspect of function and performance,flexible and modifiable model and basic software tool-chains are necessary. Takingeverything into consideration, it is of great significance to research the method ofmodling processor rapidly.A high performance CPU has a plenty of choices of accumulated architecturedesign schemes after years of development. Taking into consideration of verificationprocess of high performance microprocessor in the near future, fast prototype can beused to achieve the balance between the prototype accuracy and the early demand forsoftware development. This paper completes deep research and analyses aimedprimarily at satisficing the requirements of generator processor model and softwaretools in XX project, RISC-P architecture is used to simulate the possible newmicroarchitecture design. The main content and contribution of this paper are showed asfollows:RISC-P instruction set is designed on the research of a various of Instruction Sets.The instruction set includes data process immediate instructions, data process registersinstructions, mul-add instructions, load/store instructions. Besides, RISC-P architectureprocessor is designed on the foundation of the RISC-P Instruction Set.Two levels of abstraction processor model including instruction set accurate andcycle accurate processor model are descripted in LISA language. Software tool chain ofthe self-definition instruction set, processor RTL source code as well as scripts for EDAtool are generated based on cycle-accurate simulation model by Processor Designer tool.What is more, RTL code is synthesized in45nm process by Design Compiler tool inthis paper. The proposed microarchitecture prototype achieved the frequency of334MHz,25.9174681mW power,0.5894mm2of die area.Following the principle of redundancy verification, microprocessor model’ssimulation and debugging that is based the PD platform,as well as the logic verificationfor generated RTL code by soft simulation and hardware-accelerated verification, arecompleted in this paper. It has been proven by the result of variable verfication method that the processor model that is based on the fast prototype method can achieve nicetradeoff of simulation accuracy and structure flexibility.Just taking an example of design adjustment of memory capacity and addingbranch prediction component, fast prototype method is proven to be capable ofsupporting DSE flexibly. Combined with Synthesis tool and vendor technology library,this method can evaluate the impact on area, frequence and power-consumption ofdesign adjustment. Furthermore, architecture simulation tools can be used for softwaredevelopment and performance evaluation of specific software applications.This paper explorers the application of fast prototype method in the fileds ofmicroprocessor design and verification on the flatform of Processor Designer Tool incondition of custom RISC-P architecture documentation. The experiment process andresults have shown that the method is competent for rapid design modeling, architectureparameter space exploration, functional verification and software applicationsdevelopment, as well as the physical design performance evaluation.