Research And Implementation Of Parallel Timing Recovery For Digital Receivers

With the advent of information age, information transmission rate is higher andhigher, even more than1Gbps, so hardware processing speed of data is becoming moreand more demanding. Due to hardware restrictions, serial digital signal processingstructure already can not meet the requirements of high-speed communication, so designof parallel structure is necessary. Symbol timing recovery is one of the key techniques inwireless communication system, and it is the premise of the receiver gets the correctsymbol, so this paper focuses on parallel structure of this technique in high speed wirelesscommunication.Gardner algorithm is the common method of timing recovery at present. It isirrespective of carrier phase, and only needs two samples per symbol. In principle, thispaper designs the coefficient of interpolation filter and loop filter. This paper designs fourparallel timing recovery structure, and optimizes parallel algorithm of numericallycontrolled oscillator, and achieve the high speed digital signal processing by FPGA.Through ISE timing simulation, the result shows the design of four parallel timingrecovery structure is achieve the function. The maximum frequency of the structure is250MHz and it can process1000MHz data from ADC.