Design And Implementation Of The Algorithm Of Timing Recovery In QAM Receiver

With the development of digital technology and information technology, analog TV will be substituted by digital TV, and TV will step into the digital era. The digital TV can broaden the function and utility of TV, and made it possible to combine the three networks (internet, telephone network, and cable TV network) to one. It is difficult to forecast the kinds of digital production derivate from the digital TV, which will push our electronic information industry to a new stage.One of the key technologies of digital TV is timing recovery. This paper researches the algorithm and structure of timing recovery in DVB-C standard compatible QAM receiver, and the designs and implements an algorithm of timing recovery with FPGA, which is part of HDTV application. The timing recovery in this paper is composed of interpolation, timing error detector, loop filter and numerically controlled oscillator.Timing adjustment in a digital modem must be performed by interpolation if sampling is not synchronized to the data symbols. This paper analyzes the fundamental equation for interpolation, and a method for control, and outlines the signal-processing characteristics appropriate to an interpolator, and then implements a Farrow structure for cubic interpolator.Gardner's algorithm of timing error detector, which was designed for QPSK data stream, was modified in this paper, so that the algorithm can be applied in QAM receiver. The algorithm of timing error detector in this paper requires only two samples per symbol for its operation, and one of the two samples is also used for the symbol decision. The algorithm is not decision directed, and is quite independent of carrier phase.