Design And Implementation Of Timing Recovery Of The Second Generation Digital Satellite Receiver

This paper is about the algorithms of timing recovery used in the second general digital satellite television (DVB-S2) channel receiver system and its FPGA implementation.The timing recovery theory and algorithms are introduced. Their performances are analyzed. In this paper, polynomial interpolator and timing error detector are analyzed especially. The traditional interpolators including linear, PPI and Cubic interpolator are discussed. Through the simulation of these algorithms, their performance and realization complexity is analyzed. Afterward we investigate several optimal interpolation filters including minmax the worst-case phase distortion algorithm, polynomial and frequent domain optimal algorithm. Through the simulations, the two interpolators are compared with the traditional interpolators by performance. NDD-Gardner detector of timing error-detecting algorithms is analyzed in the timing recovery loop. This paper gets a timing error-detecting inproved algorithm, simulation results show the improvement of jitter performance.Based on Matlab simulations, FPGA design schemes are proposed. Finally, this paper makes a simulation of circuits with Quartus and implements FPGA-hardware.By the test in the channel, the whole circuit system obtained good performance.