Research And Design On Dynamic Reconfigurable For Multi-Core Processor Base On DSP

With the rapid development of multimedia, audio and video embedded processor capacity requirements are also increasing, and parallel programming on multicore processors for embedded development process it became a major problem. From another point of view how to break the cycle of parallel programming, how to reduce the difficulty of programming on embedded multicore platform-specific scenarios, the proposed dynamic reconfigurable technology is just one solution to the above problems. Dynamic reconfigurable processor is a new technology based partially reconfigurable technology makes embedded DSP processors can be kept switching dynamic library calls. In the absence of embedded multicore platforms nonvolatile memory, while an embedded operating system BIOS core architecture platform does not resolve dynamic function library.Can be performed on the embedded DSP processor, the file may be called collectively known as ELF file, but this type of file follow the same file format, this paper studied the ELF file format, analyze the ELF file in different fields Role and distribution, supports this theory, according to the established ELF file format, analog Linux operating system dynamic library file parsing process, designed framework can be applied dynamically reconfigurable multi-core platforms. This article will be divided into dynamic library dynamic reconfiguration frame memory, dynamic libraries for parsing and multicore communications three modules, respectively, while the code is implemented the three modules.Meanwhile this paper Key Stone architecture of TI's TMS320C6678, Key Stone II heterogeneous multicore platform architecture Both development board made a thorough research, introduces embedded multicore processors in a variety of communication mechanisms. Analysis of the above-mentioned two processor memory architecture and dynamic reconfigurable frame memory access patterns, describes the content of dynamically reconfigurable framework for the efficient use of great help. Since the multi-core processor platform is generally controlled by the host computer to use, and the docking mode heterogeneous platform there are many, dynamic reconfiguration framework for ease of use and scalability, the internal framework to achieve a variety of heterogeneous platforms docking mode, such as PCI-e bus, Ethernet, SRIO and so on. Different ways for different hardware platforms, at the same time, different tactics has a different system performance.In this thesis, each module is tested.In the embedded multicore platforms and master different connections, dynamically reconfigurable frame reception speed DLL files. When calculating a plurality of task context switching speed, testing the effects of different memory access patterns used to frame. After the test results show that the framework can be completed multicore reconstruction, while switching delay dynamic library processor after 10 ms.