Digital Decimation Filter Design For Sigma-delta ADC

Compared with the traditional Nyquist ADC, Sigma-Delta ADC has theadvantage of high precision, high speed. Sigma-Delta ADC’s development isinseparable from two major technology development, oversampling technology andnoise shaping technology. Using the oversampling theory push the noise out of thesignal band, and the noise shaping technology can improve the signal to noise ratio.Sigma-Delta ADC is composed by Sigma-Delta modulation and digital decimationfilter. The oversampling technology and noise shaping technology make Sigma-Deltamodulator more and more simple but increase the requirements of the digitaldecimation filter. The post-stage filter decimation should not only filter the noisebeyond the frequency band, but also down-sampling the output of the modulator.Since the digital filter is the largest part of the whole chip consumes power and area,the study of the decimation filter has important significance.This paper is based on14bits,128times sampling rate modulator. The designgoal of the paper is doing128times sampling of the input signal, and output theNyquist frequency. The design requirements for each level as follows,bandpass rippleis less than0.01dB, stop-band attenuation is more than110dB and output precision isnot less than14bits. This paper first did a thorough study on the Sigma-Deltamodulator’s principle, the oversampling and noise shaping technology, then accordingto the structure characteristics of the modulator choose the suitable filter structure torealise drop sampling and filtering. In order to reduce the area and powerconsumption, chose the multi-stage filter as the whole structure of the decimationfilter. Considered the first level requirement of down-sampling significantly, selectedCIC filter as the first level. In order to make up for bandpass attenuation, then thesignal was drop sampling by one time. The second stage selected the CICcompensation filter, the third stage chose the half-band filter to reduce the output signal to Nyquist frequency. Half-band filter belongs to FIR filter, and half of thecoefficient is zero, the structure is simple, conform to the requirement of design. Builtthe decimation filter then simulated use the Matlab at the same time, validate itsfeasibility in theory. In order to realize the function in hardware circuit, select theVerilog code, and proved the correctness of the code through the ModelSimsimulation result. At last realize the hardware circuit through the ASIC back-end. Inthe ASIC implement stage, mainly analysis the static timing problem, do a detailinstruction about the definition of start point and end point, as well as the setup timeand the hold time in the timing paths. Carry out a detailed analysis about the timingviolations of the paths, and how to manually solve timing violations. At last, importthe created layout into Virtuoso. After the DRC and LVS rule, checking to ensure theaccuracy of generated layout and finally got the final layout.Tools used in this article as follows: Matlab (Version R2010a), ModelSim(Version6.2b), Synopsis company’s Design Compiler(Version D-2010), Formalit-y(Version B-2008), Cadence company’s Encounter(Version6.20), Virtuoso(Vers-ion6.1.4), etc. Used technology is0.35μm.