High-performance Sigma ¡÷ Adc Design

Oversampled ADCs based on sigma-delta ((() modulation are well-suited to the implementation of analog interfaces in digital communication and signal processing systems. These converters exploit the enhanced speed and circuit density of modern VLSI technologies and overcome limitations on resolution that result from the component mismatching. Now sigma-delta ADCs have been widely used for high resolution A/D conversion.The principles of oversampled ADCs are discussed firstly. Then the architectures and design methods of broadband sigma-delta modulators are studied. Based on it, the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed. A new method is proposed to minimize the effect of kickback noise of the comparator on flash ADC. Two different architectures of sigma-delta modulators with 700KHz bandwidth and 14-bit resolution are designed using two different technologies. One modulator uses 2-1-1 multibit architecture with fully differential switched capacitor circuits, whose oversampling ratio is 16 and sampling frequency is 25MHz. It is implemented in the CSMC 0.6(m CMOS process with double-poly and double-metal. It operates under a single 3.3V supply and the output range of the quantizer is 2V. Simulation results show that the modulator achieves the resolution higher than 14bits and consumes about 76mW. Another modulator uses 2-1-1 single bit architecture with fully differential switched capacitor circuits, whose oversampling ratio is 32 and sampling frequency is 50MHz. It is implemented in the UMC 0.18(m CMOS process with single-poly and 6-metal. It operates under a single 3.3V supply and the output range of the quantizer is 2V. Simulation results show that the modulator achieves the resolution higher than 15bits and consumes about 90mW.The resolution and conversion speed of sigma-delta ADC are determined by the performance of the modulator, but its area and power consumption are mainly determined by the decimation low pass filter. The principles and design methods of the decimation filter are studied. Furthermore, the ways to optimize the circuit architecture and improve the circuit performance are analyzed. A number of design techniques are used to decrease the area and power consumption of the filter, including the way to determine the input and output wordlength of the filter in each stage and the method to find the adder length when the filter's coefficients are represented in CSD. Finally, an FIR decimation filter used in 14bit 1.5625MHz Nyquist rate oversampled ADC is designed. Considering the finite wordlengh effect of input signals, coefficients and intermediate results, simulation results shows that its passband is 700KHz, stopband is 862.5KHz, the ripple at 1KHz is 0.0005dB, the ripple at 700KHz is 0.013dB, and the attenuation at 862.5KHz is 86.1dB when the input sampling frequency is 50MHz and the output sampling frequency is 1.5625MHz.