Digital Filter Design For 16-bit 100Ksps Sigma-Delta ADC

The research and design of digital filter in Sigma-Delta ADC is introduced in the paper.In recent years, audio and video has entered the digital area.CD,DVD,MP3 and other digital electronic equipment become hot in the consumer electronic market. Meanwhile, along with VLSI(Very-large-scale integration) technology,on one signal chip integrated complexity of the digital signal processing capabilities has become possible,the study on the audio system DAC chip has great practical significance.Sigma-DeltaADConverter, a kind of oversampling Analog-to-Digital Converter,with high resolution and low transition rate,is mainly applied in the field of audio and video signal processing and well-suited to the implementation of analog interfaces in digital communication and signal processing systems.These converters exploit the enhanced speed and circuit density of modern VLSI technologies and overcome limitations on resolution that result from the component mismatching. Now Sigma-Delta AD Converters have been widely used for high resolution A/D conversion. Generally, the analog part in a Sigma-Delta AD Converter modulator mainly decides design resolution and transition rate. While the transition rate,power dissipation and chip area of a digital filter,which is the digital part,also has large influence on the performance of A/D or D/A Converters.The principles and design methods of the decimation filter are studied. Furthermore,the ways to optimize the circuit architecture and improve the circuit performance,decrease the area and power consumption are analyzed,including the design methods of multi-phase structure, TDM(Time Division Multiplexing) and reused module. The way to change normal CIC(Cascaded-Integrated-Comb) filter for non-recursion CIC and Multi-stage multi-rate signal processing are used to implement compensation low pass and half-band filters and the method to find the adder length when the filter's coefficients are represented in CSD(Canonic Signed-Digit).Finally,a FIR filter used in 16bit 100KHZ Nyquist rate oversampled ADC with specific SNR (Signal to Noise Ratios)at 98db is designed. Based on an analog Sigma-Delta modulator with 3-order cascaded structure,the filter consists of CIC filter and narrow transition-band FIR (Finite Impulse Response)filter. The whole design stars from Matlab system simulation,Verilog HDL RTL coding,Modesim SE RTL netlist simulation and gate level netlist simulation,Synopsys Design Compiler synthesis,Encounter place and route. The system design is based on verified with FPGA(Field Programmable Gate Array) board,and implemented in the CHRT 0.35μm CMOS process with chip area 2.5×2.5m 2.All above make decimation filter considered as a standard unit in ASIC library to work together with modulators.