Design And Implementtation Of S+Core Simulator

S+core is a 32-bit RISC(Reduced Instruction Set Computer) with Sunplus-owned instruction set architecture (ISA). The ISA has 32/16-bti hybrid instruction mode and paralel conditional execution(patent pending) for high code density, high performance and versatile applications.Simulator has become a very imporment tool in CPU design and system software development. The main benfit of the full-system software simulator is the rapid developed, low cost and easy mantiain. Simulator can help architecture optimization and software-hardware codesign, and also can help system software develop and optimization. Speediness, high precision and easy to configure and modify is the main features of a perfect simulator, but it is difficulty to got them all at the same time, because they are conflict with each other.Fistly, the popular simulation technologies are discussed and the differences between them are analyzed and compared in detail In this paper. Analyzing the dynamic binary translation thchonology, which can enhance the running speed of simulator and some key technologies about simulator are studied. Secondly, analyzing the S+core CPU architecture,to make user have perceptual knowledge. Base on the S+core CPU architecture and the simulation technologies, the S+core simulator was designed and implemented.The most import feater of the simulator is the simulator's running speed. Tt is the first restrictive condition to make simulator widly aplied. In this paper, reseach the key thehnology of simulation, describe how to combination the features of S+core architecture and the features of S+core application environment, use two simulation technologies, interpretation technology and dynamic binary translation thchonology to implement the S+core simulator which has the high performance and high precision. At the same time designed and implemented the debug interface for gdb application, designed and implemented the device interface for varied SOC using S+core core. Implemented the Timer, LCD device. And introduce how S+core simulator successfully applied in Sunplus IDE.