.10 G-epon Physical Layer Design And Realization

This paper specifys the implementation of PCS sublayer of 10G EPON system,which is based on FPGA and IEEE802.3av protocol.Firstly,it introduces the development for the technology of Ethernet and Access Networks.Secondly, giving the presentations for the the realization for ESL model which is used in the system design and implementation.And then,it emphasizely give the methods for designing and implementing the kinds of PCS logic fuctions.Lastly,giving the verification and testing for the design uint based on EDA and FPGA,which including the test schemes and figure results for verification and testing.Solutions for all the key modules in the down stream process of PCS sublayer are given based on FPGA,such as synchronization modules,scrambler/descrambler modules,64/66B encode/decode modules,gearbox modules,bandwidth adaptive modules and FEC encode/decode modules in OLT and ONU.In the end ,it is successful to realized the logic fuctions which is defied by IEEE802.3av.The method of Top-down is applied to the design.Study and research hard for the technology protocols, and then work out for the logic specifics for each module.Later,it is the time to do the high level design and low level design.At last,all the logic fuctions are implemented,which is using Verilog programming.Besides, the design unit also has been verified and tested, which is processed synthesis and layouts in ISE10.1. The opposite method is selected in the verification schedue for the design unit, which is called Down-top. At first, it is try to ensure the fuctions of the children modules is met to the logic specifics through the unit test.And then it does the integrated test in data path and protocol path in PCS sublayer.At last,it processes the system test based on the ESL modle,which is to prove that all the modules in the 10G EPON are designed well to reach the perfomances,such as registered automatally,telemete,MPCP protocol processing and so on.Finally, the 10G EPON PCS logic designed in this paper is tested on base of Xilinx Virtex5-330T FPGA platform, including all kinds of system logic function, system performances and interoperability. Test result shows that the design of 10G EPON system realizes the standard features stipulated in the agreement of logic function characteristics, including line rate constant, high-speed stream dynamic balance, a fixed delay, bandwidth conservation etc. In addition, high-speed self-locking and low BER also reach specified performance index required by IEEE802.3av, which provides a guarantee of the application system for 10G EPON space expansion.