Based Channel Equalizer In The Fpga Design And Implementation

In radio communication system, because of multipath effect and the finity of channel bandwidth and incomplete channel, intersymbol interference (ISI) is inescapability during the data transfer. In order to eliminate ISI and noise, equalizer has to be used in the receiver. Blind channel equalizer can reduce the ISI without the assistance of the transmitted sequence. The received data sequence is only needed by blind equalizer to equalize the channels. Bussgang blind equalizer algorithm is used in this dissertation, because its convenience of real-time implementation and thinkable performance. This dissertation consists of designing and implementing a blind equalizer system that is compatible with Bussgang blind equalizer algorithm using FPGA (Field Programmable Gates Array) in standard hardware description language Verilog. The conception of DDLMS (Decision-Directed LMS) and CMA(Constant Modulus Algorithm), which are branches of Bussgang algorithm, and the flow of FPGA design are firstly introduced. Design principle , structures and Verilog implementations of modules in enhancement blind equalizer are described in detail in follow sections. Each section closed with the structure graph and the test results of module in verification. This thesis investigates the design technologies of EDA (Electronic Design Automation) by means of designing and implementing blind equalizer. It provides preliminary study for large scale SOPC (System on Programmable Chip) in wireless communication system field.