Design And Verilog Implementation Of Digital Equalizer

With the progress of digital signal processing and integrated circuit technology, digitalcommunication has stepped into a high speed and high reliability stage. Inter symbol interference(ISI) is generated when digital signal is transmitted through a channel with non-idealtransmission characteristics, resulting in the increment of signal noise ratio (SNR). Equalizationtechnology is usually used to eliminate the ISI. Adaptive equalization technology can trace timechanging channel to reduce the adverse effect from ISI and noise to the communication quality.So an equalizer is very necessary in receiver block of a communication system.The mechanism of generation and elimination of ISI and the principle of equalization isdiscussed in this dissertation. Algorithm of zero-force, LMS, VSS-LMS and RLS is analyzedfrom the viewpoint of both theory and computer simulation. It is found that VSS-LMS with a γvalue0.00048can improve the convergent speed of LMS algorithm. Compare with RLS, LMShas a slower convergent speed. For its simple structure, LMS is easy to implement on hardware.An adaptive equalizer based on LMS algorithm is designed with Verilog HDL languageused top-down method. Design idea of top module and detail describe is provided and elucidated.It is shown that with Modelsim simulation confirmation, this equalizer is effective in adaptivefiltering. Finally, the design is synthesized and realized on Altera Cyclone II EP2C5T144C8withQuartus II.