Wireless Channel Emulation And Fpga Design Of The Equalizer

As one of the most powerful means of modern communications, the technique of radio mobile communication has been deeply approached and kept quickly developing. In radio communication system, because of multipath effect and the finity of channel bandwidth and incomplete channel, intersymbol interference (ISI) is inescapability during the data transfer. In order to eliminate ISI and noise, equalizer has to be used in the receiver. Blind channel equalizer can reduce the ISI without the assistance of the transmitted sequence. The received data sequence is only needed by blind equalizer to equalize the channels. This dissertation mainly discusses the design and realization of wireless channel blind equalizer based on FPGA. The joint decision direction least mean square(DDLMS) and constant modular algorithm(CMA) is selected. The structure of the equalizer contains four quadrature finite impulse response(FIR) filters. During the process of the design we simulate the algorithm by the MATLAB software at first, then the Verilog HDL programs were wrote for realization on FPGA. In the design flow of hardware description language, one of the design ways, Top-Down, was used so as to shorten the design periods and enhance the expansile performance. The test result denotes that the equalizer's performance arrives at the anticipate targets. This thesis investigates the design technologies of Field Programable Gate Array(FPGA) by means of designing and implementing blind equalizer. It provides preliminary study for large scale SOPC (System on Programmable Chip) in wireless communication system field.