Research On Simulation Technology Of Multi-processor Communication In System-level Simulator

System-level simulation plays important roles in verification of functional completeness and defect analysis. It should be paid more attention to the analysis about coupling and communicating among processors, especially when to simulate the Multi-processor embedded devices on system level.The technology of hierarchical design is adopted to construct the overall framework of system-level simulator. it divides the framework into three layers including Plug-in layer, control layer and application layer. Enclosing the key problem of communication simulation among processors, the thesis starts with the analysis about communication modes among processors, constructs a communication plug-in functional model in a uniform form for different communication modes, and designs a unified structure of communication plug-in. The solution which combines pin interconnection with pointer join is adopted to connect the processor plug-in with communication plug-in. The global clock synchronization mechanism is introduced to guarantee the timing relationship of system-level simulation.The communication plug-in functional model is verified by means of the classical cases such as FIFO memory plug-in and I/O plug-in. At last, the thesis adopts plug-in assembly method to build a system-level simulator for multi-processor, and then test the performance of communication plug-in. The result shows that the communication plug-in has good reliability and efficiency.