Research And Implementation On SCI Serial Communication Interface Based On FPGA

The national 863 project "Development of FC board for the Flight-controlling computer system" is to design an FC board compliant with CPCI bus standard. This subject is the further extension of the project, which is to design SCI Serial Communication Interface for high-speed serial communication among multiprocessor systems.Under this background, the SCI Serial Communication Interface is researched and designed in this thesis. The SCI protocol is introduced in general, the function and implementation of the two modules of the SCI Serial Communication Interface, SCI node module and CPCI Bus Interface, are also discussed.SCI node module includes Aurora WR module, Interrupt Process, bypass FIFO, sending and receiving RAMs, address decoding module, and MUX. It uses the resource in the FPGA to implement the SCI-node model. It is with the RocketIO to implement the high-speed communication and with Aurora IP core to implement the Aurora link layer protocol. Design a synchronous FIFO to implement the bypass FIFO. It is with the block RAM to design the sending and receiving RAMs. The Interrupt Process, address decoder and MUX are implemented in the control logic.CPCI Bus Interface include PCI core, the configuration module and user logic. In this thesis, implement the CPCI bus interface with FPGA+PCI soft core. PCI core as the bridge of PCI bus and user logic; throw the configuration module, can get the PCI core which user expects; and user logic with responsibility for the whole Communication Interface's interior logic. Then import the interrupt mechanism to improve the speed between SCI Serial Communication Interfac and PC.This design uses Verilog HDL,VHDL and Xilinx ISE7.1 to complete the design, synthesis, place&route, and processes function and timing simulation in Modelsim, and uses Chipscope Pro embedded in ISE to analyze the design online. The WinXP driver for SCI Serial Communication Interface is write by using DriverWorks; and uses VC++ 6.0 to develop the test program. Finally, the system is downloaded to the development board and work well after being verified and implemented.The reason of the low transfer-speed is discussed at the end of this thesis. It also points out the problems and the further work.