Design And Implementation Of Embryonic Circuit Oriented To Self-repair On Chip

The self-diagnosis and self-repair of a digital system on chip are a difficult problem and academic frontal for the fault-tolerance computation field by far. Inspired by the growing process of multi-cell organism embryonic circuit is a kind of digital circuit capable of self-diagnosis and self-repair which consists of a homogeneous 2-Dimension electrical cell array. Such an array is named Embryonic array. This thesis was dedicated to the research on the architecture, self-repair mechanism and the cell circuit design of embryonic circuit oriented to self-repair on chip. The structure of the main component module in a cell was improved including logic block and configuration memory. Cell-elimination mechanism was achieved by added self-repair assistant circuits. So the embryonic circuit can obtain better fault-tolerance with fewer resources. A 4-bit adder subtracter and a module 8 counter were presented as practical examples to illustrate the design method of application circuits based on embryonic array. The effectiveness of the improved cell circuit design scheme was validated by experimental results. The main research achievements of this thesis were as follows:(1) The structure of the main function modules in a cell was improved after summarizing the traditional design methods of the main modules in a cell. The logic block which could act in three different operating modes was designed. Compared with logic block based on LUT with four inputs and one output, the new logic block structure displayed improved flexibleness and resource utilization ratios.(2) Aiming at the problem of large resource consumption of configuration memory based on LUT, the structure of configuration memory based on shift register was designed. Compared with configuration memory based on LUT the new configuration memory structure strengthened the universality of cell structure and had more advantages in resource consumption of configuration memory when implementing a large embryonic circuit.(3) Aiming at the disadvantage of low spare resource utilization ratios of column-elimination mechanism, cell-elimination mechanism was achieved by adding self-repair assistant circuits to a cell. Two cell-elimination schemes were presented based on the two configuration memory structures. Compared with common column-elimination mechanism, the embryonic circuit based on cell-elimination mechanism displayed higher resource utilization ratios, stronger fault-tolerance and better flexibility.