Design And Realization Of IIR Filter Based On FPGA

In the modern electrical system, such as communication message, video frequency and image processing systems, there are often real-time and flexible requirements for meet the demand for the two aspects in the same time. Along with the development of PLD device and EDA technology, the advantage in the performance, cost, flexibility and power consumption standed out, the signal processors based on FPGAs have been applied to various signal processing fields.This paper presents the design and realization of IIR filter based on FPGA. At first this paper discussed the adder, multiplier and MAC of the basic DSP algorithm in terms of resource utilization and speed, discussing how to improve the speed of MAC with distributed arithmetic algorithm. Then according to the characteristic of basic framework of IIR filters and the scale of the LUT in the distributed arithmetic algorithm is so large, the thesis reduces it with the use of multiple coefficient memory banks and cascade mode or parallel mode, and the combination of the parallel and serial scheme is implemented in paper, and realize a ten steps low pass IIR filter connected in serial. The design is adopted to the parts EP1C6Q240C8 of the Altera Cyclone serial FPGA, synthesized and simulated with the QuartusⅡ. The result of the simulation is analyzed an compared with the theoretic value calculated by Matlab, and it proved that the function of the design is correct. At last, this paper designed a hardware circuit, use the multiple frequency square mave as the input signal to check the actual effect.The experiment prove that the scale of the design is small, which proves that the improvement on DA arithmetic is effective. And the highest system clock can reach 80MHz after the improvement. The design indicates the flexibility at realizing the low-pass, hign-pass and band-pass filter easily just through some modifications on IIR filters LUT respectively.