Research Of SW/HW Co-design Of Unified Decoder For H.264 And AVS Based On ARM ESL Platform

High definition H.264 video technology is widely used nowadays, but the payment for the license fee is huge. AVS video standard is published, therefore there are more and more researche efforts in H.264 and AVS, one target is to achieve the high speed of decompression on the basis of ensuring the encoding quality is not influenced.We propose a new hardware/software co-design method based on ARM ESL platform. This method is used to design and verify H.264 and AVS video decoder via simulation. In HW/SW partitions, the luminance interpolation is implemented in hardware with combination of the half and quarter-interpolation. The functions of loopfilter in H.264 and AVS are combined. This paper also presents the improvement of loopfilter hardware architecture and the incorporation of DMA Controller. All these lead to better overall system performance. In the experiments, we compare the simulation performance of decoder implementations to decode an AVS stream whose resolution is 720x576. These implementations include the pure software versus the SW/HW partitions. The results show that SW/HW partitions solution provides better overall performance. We believe our work serves as a useful reference for AVS designs with HW/SW partitions.The major target of the project is to evaluate overall real time performance of the decoder at system level. By analyzing the timing cost of H.264 and AVS code, we find the interpolation module is located at the bottom layer of functions. The interpolation module has the characteristics such as high time costs, high computation complexity, easy division between software and hardware, high parallelism and low hardware costs.