Research And Implementation On Software-Pipelined Eliminating Technology In IA-64 Binary Translation

Software pipelining is a kind of technique that could be used to develop instruction level parallelism for loops, it speeds up the loop by overlapping the execution of several consecutive iterations. However, the restriction of hardware platforms places great effect on migrating code between different platforms. As far as we know, all existed binary translators in the world do not deal with the problem of 64-bits software pipelining. Therefore, translating binary code with the pipelining characteristics of 64-bits architecture brings new challenge for binary translation technique.This thesis grounded on the software-pipelined mechanism of IA-64 illustrates that the goal of removing the software-pipelined characteristic should be reversely convert the optimized code after software pipelining on the source machine into a semantically equivalent sequential counterpart with no dependence on the hardware; on the basis of thorough research in the features of IA-64 architecture, we presented two algorithms to eliminate the software-pipelined characteristics based on the semantics of software-pipelined instruction, which guaranteed the equivalence of semantics between the original program and the converted one; with regard to the feature of software-pipelined binary code, we studied software-pipelined eliminating technology and realized it in the ITA system which is a static binary translation system of 64-bits machine developed by our group.The correctness and validity of ITA binary translation system provides verification for the contributions of this thesis. Up to now, ITA system can translate more than 1000 c programs from many testing benchmarks such as SPEC CINT2000 and NAS.