Research Of Software Pipelining Framework Based On BWDSP

BWDSP is a digital signal processor that based on clustered architecture and supports Very Long Instruction Word,which can parallel process multiple instructions in the same cycle.The clustering structure can effectively increase the instruction-level parallelism of architecture,it cannot take the extra cost of hardware.Based on self-designed processor BWDSP of optimization of software pipelining as the research topic,the main research of this thesis will be explained as follows.(1)This thesis discusses the main architecture of BWDSP,it's hardware architecture and instruction system.The article also introduces the Open64 compiler in the BWDSP processor,which details the intermediate representation structure and the back-end intermediate code representation supported by compiled of the compilation framework of the Open64 compiler.(2)Software pipelining is an important technique for back-end of compiler,it can improve the performance of program with loops.The main idea of software is to excavate the parallelism of instructions from one iteration to another.Through the implementation of the overlap of the instructions,SWP can make full use of hardware resources and improve the efficiency of the program.The main work of this thesis is to achieve the software pipelining for the backend of the BWDSP architecture for the Open64 compiler,and adopt the modulo scheduling that is classical optimization techniques of SWP.Based on modulo scheduling of SWP is added in the BWDSP platform,A new SWP optimization algorithm is proposed to deal with the problem of SWP failure caused by the dependency circle.It does analysis of the dependency circle for loop,split the reduce register into several counterpart duplicates and make the loop with reduced variable pipelining favorably.Through the classical algorithm testing,experimental results show that the framework can make more loops pipelining successfully and improve performance at 58%least.(3)Based on vectorization and software pipelining of parallel optimization technique,including special memory access instruction,zero-overhead looping instruction of improving efficiency in the loop,Instruction-level Parallelism(ILP),combined with the specific function of loop characteristics,expansion for the string and memory function of instruction level parallel mining,the article achieve the optimization of String and Memory functions Based on BWDSP.The experiments results show that the optimization rates of most functions of the theory of running time of 1.5 times on hardware platform,which is of great importance to enhance of platform performance of BWDSP.