Design And Implementation Of The Software Pipelined Loop Buffer For The Innovative X DSP

Plenty of loop opearations exist in the DSP algorithm. It is an important way to improve theperformance of microprocessor by exploring instruction level parallelism between loop bodies.The scheduling technology of loop bodies includes loop unrolling and software pipelining. Thetechnique of software pipelining is studied to improve the executing efficiency of loop programsin the innovative X DSP.The software pipelined loop buffer is designed and implemented.In this dissertation, the techniques of loop unrolling and software pipelining are describedand compared detailedly. Based on the requirements and characteristics of the X DSP, a novelloop buffer is designed based on the modulo scheduling algorithm. This unit locates in thedispatch phase of the instruction pipeline, used to store and dispatch instructions of loop bodies.It reduces memory access latency and frequency to decrease the performance disadvantage ofDSPs. The main work in this dissertation are followed.1) Based on the analysis of executing characters of for loops and while loops, the wholearchitecture of the loop buffer is pictured. The control module and store-dispatch module of theloop buffer are also designed.2) A tracking and comparing mechanism of loop instructions is designed to serve for theloading, draining and reloading of instructions, Realizing the exact storage and distribution ofloop instructions.3) Two mechods of counter comparing and interrupt draining are designed to gain theaccurate interrupt of loop programs.4) Verification methods are studied. The verification platform is builded to serve thesystem-level verification of the loop buffer.5) The performance of the loop buffer is evaluated, using a matrix multiply-accumulateprogram and three typical image algorithm programs. Its utilization ratio for the above fourprograms is95.34%、90.61%、88.85%and89.94%, respectively. It decreases the frequency ofprogram memory access and reduces the dynamic power consumption of the program memory.6) Based on a45nm technology, logic synthetize is conducted for the loop buffer. Its workfrequency is up to1GHz and its area is76778.69um2. Its dynamic power is28.99mW and thecell leakage one is1.83mW.There are up to11232-bit instructions that stored in the loop buffer. On the control ofspecial loop instructions, the loop body instructions are stored and dispatched, greatlyimproving the execution efficiency of loop programs.