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Research And Design Of Ground Access System Of Satellite Based On FPGA

Posted on:2006-11-29Degree:MasterType:Thesis
Country:ChinaCandidate:H Z ZhangFull Text:PDF
GTID:2178360212983863Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
The rapid development of satellite and the rapid increase of communication capabilities, demand the data transmission system has the ability of high speed and efficient data processing and transmission. Limited by the power and the bandwidth of satellite communication system, the technique of forward error correction is adopted to provide more efficiently, better transmission bit rate and lower bit error rate data transmission. For this, the ground system must have the ability to achieve high speed error correcting.With the appearance of the system-on-programble-chip(SoPC) , the system design become more flexible. The device is designed in a way that all the important function modules, including synchronous, descrambler, RS decoder, Ethernet access could be integrated in one programmable logic device (PLD). This brings the advantage of chip number reducing and upgrading ability increasing. The designs for every modules would be implemented in the TOP-DOWN( from top to down)way.The paper used the SoPC approach to design the satellite baseband data processing system. In order to fulfill the application for high speed information processing and complicated controlling in Ethernet data access, we study up on SoPC in this paper and implement an embedded system in FPGA by using microprocessor IP core.
Keywords/Search Tags:SoPC, IP Core, FPGA, Synchronous, Ethernet, Reed-Solomn Encode and Decode
PDF Full Text Request
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