Design Of Key Modules For 400Gbps Ethernet TX PCS

With the rapid development of information technology and the emergence of emerging services such as big data,the user's demand for higher bandwidth and scale networks are more and more strong.In response to the rapidly growing demand for high-speed and network-loading capabilities in core networks such as data centers,Ethernet is moving toward higher speeds.With the promulgation of the new generation of 400 Gbps Ethernet(400GbE)standard IEEE 802.3bs,the transformation of the next generation of mobile networks has arrived.At the same time,the transmission of high-speed signals also poses a challenge to the design of the Ethernet Physical Coding Sublayer(PCS),and the increation of functional modules makes the design more difficult.This thesis studies the key module design and FPGA implementation of the400 GbE transmitter PCS based on the 25Gbps×l6 architecture in the IEEE802.3bs standard.This thesis adopts a top-down design method,the main functional modules of PCS,including 64B/66 B encoding,FIFO buffer,256B/257 B transcoding,scrambling,alignment mark mapping and re-insertion,FEC pre-interleaving,RS coding,and the embedded actuators has been implemented based on Verilog,additonally the simulations and verifications were performed.In order to improve the performance of the circuit,the parallel coding technology and pipeline technology are optimized for the scrambling module,which reduces the delay of the circuit.The pre-interleaving module is implemented with registers.While completing the data interleaving function,it also realizes the connection of signals in different clock domains.To facilitate FPGA implementation,the two RS encoders are composed of64 coding modules,which work in parallel.A processing rate of 400 Gbps is achieved.The design of this thesis has been implemented on Xilinx FPGA.The thesis gives the integrated circuit diagram and simulation waveform,and gives the timing report and resource utilization after the implementation of the whole PCS.The simulation and implementation results show that the PCS circuit designed in this thesis has the correct function and the timing meets the requirements.The highest clock frequency reaches 415 MHz and the total speed can reach 425 Gbps,which meets the requirements of 400 GbE.The research in this thesis can be applied to ultra-high-speed Ethernet communication,and has certain reference value for the development and application of high-speed wired communication in China.