A Congestion Driven High Level Re-Synthesis Method After Floorplanning

Interconnect is becoming one of the dominant factors affecting VLSIperformance in this deep submicron era. Although along with the routinglayers increase and the routing resource will be more abundance, the localcongestion can still not be avoided because of more complex circuit designand higher requirement of performance. In the traditional VLSI design flow,the high level synthesis stage of the front end and the physical design stage ofback end are completely separated. Nothing about routing congestion isconsidered in the high level synthesis stage. And there is no optimization tothe result of high level synthesis for routing congestion. This will result thatthe physical design stage takes great pressure, and even fails to solve allcongestion. Because the circuit topological structure which has greatinfluence upon routing demands distribution is decided by high levelsynthesis, and can not be modified by physical design. Once the physicaldesign tools fail to solve congestion, it has to restart the flow from the verybegin and do the high level synthesis again. This is a time-consumingprocedure which can not guarantee convergence.This paper has made some improvement of the traditional VLSI designflow. It combines the physical design and the high level synthesis through ahigh level re-synthesis method to consider the routing congestion problem inthe high level. With this method, the routing demands have been distributedon the chip as evenly as possible before the physical design starts. So theprobability of routing congestion is kept in the lowest level, and evencongestion occurs, there is enough space for physical design tools to fix it.The big iteration loop is removed in the new design flow.A novel congestion driven high level re-synthesis method afterfloorplanning is presented in this paper. First, the information about theposition of modules is got with the floorplanning tool. And then thedistribution of routing demands is calculated by a probability module andeven degree of distribution of routing demands is evaluated. At last thetopological structure of the circuit is modified by the high level re-synthesisstage to distribute the routing demands evenly on the chip. This algorithm issimulated annealing based.The experimental result show the routing demands can be distributedevenly on the chip successfully by our algorithm.