Using Of Symbolic Polynomials And Interface Synthesis On High Level Synthesis

The design complexity and system function of electronic system have been increasing largely, and the competition from the global also shortens the design period. Therefore, the demand for the tools of electronic design automatic is tremendous and the requirement for efficiency of EDA tools is more and more precise. All of this promotes the updating of the electronic design methods and tools in some cases.Currently, existing high-level tools are effective in capturing HDL models of the hardware and mapping them into control/data flow graphs(CDFGs), performing scheduling, resource sharing, retiming, and control synthesis. However, most high-level synthesis tools cannot automatically synthesize data paths such that complex arithmetic library blochks are intelligently used. In this thesis, Grobner Basis and Buchberger's algorithm are introduced as the backbones of our reseach. It is followed that two improved dataflow mapping algorithms are presented. One of them improves minimal component decomposition algorithm. It maps dataflow sections of a high-level specification of the design to pre-optimized arithmetic library elements mostly for purpose of minimizing number of component. If there are several solutions, the algorithm selects the solution which component consumes least sum of power. But in much application, the power is more important than the other factor. So, the other of algorithm is presented that is decomposition algorithm for minimal power consumption. The object of the algorithm is minimizing power consumption. The algorithm use symbolic polynomial manipulation techniques as guideline for side-relation selection. The resulting algorithms enhance the capabilities of current high-level synthesis tools and designer's productivity.In order to automate design reuse, methods for composing system component must be developed. It is following our research for automating theprocess of generating interfaces between hardware subsystems. The basic purpose of an interface is to facilitate the movement of data. Data could be addresses, commands, values destined for a memory location, or some combination of these description. In order to allow hardware subsystems that follow different protocols for moving data to ommunicate with one another, the method presented here maps these protocols into a standard communication scheme. This scheme is then implemented in an interface architecture that is general enough to accommodate the requirements of any target interface. The method can be used to generate a cycle-accurate, synchronous interface between two hadware subsystems given an HDL model of each subsystem.