Research Of Hall Sensor And Circuit Design

Hall sensor is one of most widely used magnetic sensor. It can be not only used for magnet measurement,but also for the measurement of current, speed, position, angular. This thesis is based on the research of the performance of hall sensor, and designs a chip that is used in the detection of the cover of the cellphone.At first,this thesis introduces the development of analog integrated circuit including the function of analog integrated circuit, why digital circuit can not replace analog circuit, and the feature analog circuit compared with digital circuit, analog process technology, and the develop trend of analog circuit. Then, introduces the principle of hall sensor, the develop period of hall sensor.In chapter 2, firstly introduces the characteristic of hall sensor including sensitivity and input resistance, secondly introduces the the optimization of hall sensor including shape optimization and layer optimazition and the nonideal effect of hall sensor including back-bias effect, top-plate effect, temperature effects and parasitic.Then introduce the typical application of hall sensor .At last introduce the whole structure of the hall sensor designed in this thesis.In chapter 3, introduces the offset voltage and low frequency noise, and analyzes three ways to cancel offset voltage: muti-plate method, DDA method, spinning current method. This is the key technique of hall sensor.In chapter 4, introduces the design of switch hall sensor chip that used in the cover detection of cellphone. The design of this chip is based on CSMC(0.5um) technology. Secondly, introduces the HSPICE model of hall sensor, clock circuit design, bias circuit design, operational amplifier design, comparator design, switch design, divide resistor design and the generation of digital logic signal and so on. At last, gives the layout design of hall sensor.This thesis proposes a magnet detection method with no relation to the polar of magnet and a bias compensation method, a novelty sample circuit and a new method to reduce the power dissipation of the whole chip.