VLSI Design And Implementation For Low-complexity LDPC Decoder

Low-density parity-check(LDPC) codes originally discovered by Gallager in 1962 and rediscovered by MacKay in 1995. Recently, it have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been chosen to be part of several practical applications such as IEEE 802.11n WLAN and IEEE 802.16e WiMAX systems.,and will have a wide application prospect.This thesis presents a low-complexity decoder design for Quasi-Cyclic LDPC codes for IEEE 802.16e WiMAX system. Firstly, the relevant fundamental of channel coding theory is introduced, and some populate LDPC code decode algorithms are analysed, they are simulated in the Matlab platform, and the Min-Sum Algorithm is choosed for this decoder design, meantime, the maximum iteration number and fix-point wordlength is determined. Most attention is pay on designing and optimizing the decode's architecture. On the whole, this design adopt a partial parallelism architecture. Four design techniques is proposed for this design: reordering of the base matrix, overlapped operations of main computatinal units, early termination strategy and distributing storage method. Based on overlapped decoding mechanism, the decoding latency can be reduced 31.25% compared with non-overlapped method, and the hardware utilization ratio can be increased from 50% to 75%. Besides, the early termimation strategy can dynamically adjust the number of iterations when dealing with communication channels of different SNR values.This decoder is synthesised in Design Compiler with TSMC 0.13μm CMOS technology. The measured results show that the maximum operating frequency is 76.9MHz and the corresponding power dissipation is 85mW. The throughput achieve 55.9Mbps~68.4Mbps, and satisfy the need for IEEE 802.16e WiMAX system.