On-chip Network Interface Reliability Design

The reduction in feature size and the increase in integration have led to increasing design complexity for digital chips.Integrating multiple cores on the same chip has become the norm in digital design.The increase in the number of cores places higher requirements on the scalability and bandwidth of the interconnection system.Communication problems have become a major bottleneck for many-core chip designs.Because of its good scalability and wide bandwidth,Network-on-Chip has quickly attracted the attention of researchers and has become the mainstream solution for intercore connectivity in many-core systems.Ntework-on-Chip is mainly composed of two components,a router and an on-chip network interface.The on-chip network interface has a very important role as a channel connecting the local node and the on-chip network.With the development of integrated circuit technology,reliability issues have gradually become an important issue that hinders the development of the chip.On the one hand,the reliability requirements of complex systems are constantly increasing.Any small fault in the system may cause the entire system to fail.On the other hand,aging effects such as particle collisions,electromagnetic crosstalk and other physical factors,electromigration,and hot carrier injection,etc.,affect the reliability of the device under a small process,which makes the reliability study of great significance.This paper studies the reliability design of the on-chip network interface,proposes a new fault-tolerance scheme and test strategy,and improves the design reliability.First,this paper studies the basic structure and function of the on-chip network interface and finds that the area occupied by the asynchronous FIFO in its internal structure exceeds 50%.For this feature,a folding fault tolerance method is proposed.This method can greatly improve the fault-tolerant capability of the asynchronous FIFO,thus improving the fault tolerance of the entire on-chip network interface.Because this faulttolerance method is fault-tolerant by improving the control logic,the area overhead introduced is not large.At the same time,in order to improve the performance at the time of failure,the spatial redundancy technology is introduced on the basis of the folding fault-tolerance method,so that the fault tolerance of the method is improved while the performance is not greatly affected.Experimental results show that for the asynchronous FIFO depth of 16,the proposed method can improve the fault tolerance from 4 to 11,and only increase the area of 4.18%.Secondly,this paper proposes a non-blocking test strategy based on the folded faulttolerance method.By grouping the storage units,a part of the storage units can still work under test,so that the entire on-chip network interface can be tested while working and will not be blocked during the test.The experimental results of the verification platform built by SystemVerilog show that the test strategy can reduce the impact of the test process on the performance of the entire system-on-chip.Therefore,this design can make the onchip network interface consider reliability and performance.