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The Design And Implementation Of USB1.1 Interface In USBKEY SOC Chip

Posted on:2012-07-21Degree:MasterType:Thesis
Country:ChinaCandidate:C S HuFull Text:PDF
GTID:2178330338953700Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Because of a number of merits of Universal Serial Bus, such as cheap price, easy use, simple protocol, standard interface and easily expanding of ports, it is widely used in computer interface area. So it will be necessary to integrate the USB function in different SOC systems. This paper designs and implements the USB 1.1 interface in security SOC design. The designer should combine the ability of ASIC system design and the ability of protocol comprehension in the design. So this paper has both theory and practical value.This paper expatiate the significance of security SOC in the practical life, discussed the SOC design methodology with the reuse of IP, consequently introduced the three most important bus which include Core Connect,Advanced Microcontroller Bus Architecture,Wishbone bus. We have used wishbone bus which is the simplest bus in our design.Designers always used UTMI model in their USB controller design which is advanced by Intel. We build a new controller structure which is fit to full speed transaction in this design. A model called DPLL for extract signal and transmitter clock which instanced a digital phase locked loop is used. SIE module is a controller for packet, it controlled packet receive and transmit,packet frame and decoding of PID. EPC(Endpoint Controller)module is used for endpoints control. And USB(IUSB Interface)is instanced as the interface between controller and CPU. We made system design first to mark off the signal interface and function for every sub module based on typical ASIC design. Frame every sub module according to the system design, and test every sub module's function. We emulate the whole design after all sub modules has a good function. We build a host module and a fake PHY for system emulate. At last, synthesized the RTL module on a FPGA chip and use a computer and a PHY chip of PDIUSBP11A to FPGA verification.
Keywords/Search Tags:USB Controller, Wishbone, Verification
PDF Full Text Request
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