Essential Technology Of Embodied SRAM Controller Verification

In computer systems, memory controller is one of the most important control components for data exchange between CPU and memory. Some important parameters such as data depth, data width, maximum capacity, memory type, and bank quantity of the memory chip are decided by memory controller which automatically operates the memory access requests from CPU. The access speed and efficiency have great influence on the whole performance of computer system. As a result, it is academically and practically significant to research the IC design and key verification technique of memory controller.In this text, we targeted on one SRAM memory controller applied in embedded storage system. According to the design specifications of the SRAM controller and the micro-engine, we deeply researched the principle functions and progress of the SRAM controller. The function division of access command process in controller and the procedure of sub-circuit are mainly analyzed. The analysis of the machine code format for the SRAM access instructions is also accomplished. Besides, we proposed a method to analyze the fixed length instruction set.According to the SRAM controller's gate-level netlist, we proposed a set of verification programs with high efficiency and good portability by using new technologies in the testbench design. We verified the netlist circuit of the SRAM controller in a way based on simulation.In this text, the SRAM access instructions were operated in micro-engine assemble language environment. The machine code format was concluded. Following the analysis of the functions of the netlist with Hspice, the SRAM controller's netlist was verified by running the testbench verification codes in NC-Verilog simulation environment. The results were corresponding with the design rules.